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<title>PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result </title></head>
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<h1>PMULLD/PMULLQ—Multiply Packed Integers and Store Low Result</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>66 0F 38 40 /r</p>
<p>PMULLD xmm1, xmm2/m128</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE4_1</td>
<td>Multiply the packed dword signed integers in xmm1 and xmm2/m128 and store the low 32 bits of each product in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F38.WIG 40 /r</p>
<p>VPMULLD xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Multiply the packed dword signed integers in xmm2 and xmm3/m128 and store the low 32 bits of each product in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F38.WIG 40 /r</p>
<p>VPMULLD ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX2</td>
<td>Multiply the packed dword signed integers in ymm2 and ymm3/m256 and store the low 32 bits of each product in ymm1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F38.W0 40 /r</p>
<p>VPMULLD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Multiply the packed dword signed integers in xmm2 and xmm3/m128/m32bcst and store the low 32 bits of each product in xmm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F38.W0 40 /r</p>
<p>VPMULLD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Multiply the packed dword signed integers in ymm2 and ymm3/m256/m32bcst and store the low 32 bits of each product in ymm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F38.W0 40 /r</p>
<p>VPMULLD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Multiply the packed dword signed integers in zmm2 and zmm3/m512/m32bcst and store the low 32 bits of each product in zmm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.128.66.0F38.W1 40 /r</p>
<p>VPMULLQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Multiply the packed qword signed integers in xmm2 and xmm3/m128/m64bcst and store the low 64 bits of each product in xmm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.256.66.0F38.W1 40 /r</p>
<p>VPMULLQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512VL AVX512DQ</td>
<td>Multiply the packed qword signed integers in ymm2 and ymm3/m256/m64bcst and store the low 64 bits of each product in ymm1 under writemask k1.</td></tr>
<tr>
<td>
<p>EVEX.NDS.512.66.0F38.W1 40 /r</p>
<p>VPMULLQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst</p></td>
<td>FV</td>
<td>V/V</td>
<td>AVX512DQ</td>
<td>Multiply the packed qword signed integers in zmm2 and zmm3/m512/m64bcst and store the low 64 bits of each product in zmm1 under writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>FV</td>
<td>ModRM:reg (w)</td>
<td>EVEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit intermediate results are stored to the destination operand.</p>
<p>128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM destina-tion register remain unchanged.</p>
<p>VEX.128 encoded version: The first source and destination operands are XMM registers. The second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register or 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.</p>
<p>EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.</p>
<p><strong>Operation</strong></p>
<p><strong>VPMULLQ (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask* THEN</p>
<p>IF (EVEX.b == 1) AND (SRC2 *is memory*)</p>
<p>THEN Temp[127:0] (cid:197) SRC1[i+63:i] * SRC2[63:0]</p>
<p>ELSE Temp[127:0] (cid:197) SRC1[i+63:i] * SRC2[i+63:i]</p>
<p>FI;</p>
<p>DEST[i+63:i] (cid:197) Temp[63:0]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+63:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VPMULLD (EVEX encoded versions)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask* THEN</p>
<p>IF (EVEX.b = 1) AND (SRC2 *is memory*)</p>
<p>THEN Temp[63:0] (cid:197) SRC1[i+31:i] * SRC2[31:0]</p>
<p>ELSE Temp[63:0] (cid:197) SRC1[i+31:i] * SRC2[i+31:i]</p>
<p>FI;</p>
<p>DEST[i+31:i] (cid:197) Temp[31:0]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>*DEST[i+31:i] remains unchanged*</p>
<p>ELSE</p>
<p>; zeroing-masking</p>
<p>DEST[i+31:i] (cid:197) 0</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VPMULLD (VEX.256 encoded version)</strong></p>
<p>Temp0[63:0] (cid:197) SRC1[31:0] * SRC2[31:0]</p>
<p>Temp1[63:0] (cid:197) SRC1[63:32] * SRC2[63:32]</p>
<p>Temp2[63:0] (cid:197) SRC1[95:64] * SRC2[95:64]</p>
<p>Temp3[63:0] (cid:197) SRC1[127:96] * SRC2[127:96]</p>
<p>Temp4[63:0] (cid:197) SRC1[159:128] * SRC2[159:128]</p>
<p>Temp5[63:0] (cid:197) SRC1[191:160] * SRC2[191:160]</p>
<p>Temp6[63:0] (cid:197) SRC1[223:192] * SRC2[223:192]</p>
<p>Temp7[63:0] (cid:197) SRC1[255:224] * SRC2[255:224]</p>
<p>DEST[31:0] (cid:197) Temp0[31:0]</p>
<p>DEST[63:32] (cid:197) Temp1[31:0]</p>
<p>DEST[95:64] (cid:197) Temp2[31:0]</p>
<p>DEST[127:96] (cid:197) Temp3[31:0]</p>
<p>DEST[159:128] (cid:197) Temp4[31:0]</p>
<p>DEST[191:160] (cid:197) Temp5[31:0]</p>
<p>DEST[223:192] (cid:197) Temp6[31:0]</p>
<p>DEST[255:224] (cid:197) Temp7[31:0]</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VPMULLD (VEX.128 encoded version)</strong></p>
<p>Temp0[63:0] (cid:197) SRC1[31:0] * SRC2[31:0]</p>
<p>Temp1[63:0] (cid:197) SRC1[63:32] * SRC2[63:32]</p>
<p>Temp2[63:0] (cid:197) SRC1[95:64] * SRC2[95:64]</p>
<p>Temp3[63:0] (cid:197) SRC1[127:96] * SRC2[127:96]</p>
<p>DEST[31:0] (cid:197) Temp0[31:0]</p>
<p>DEST[63:32] (cid:197) Temp1[31:0]</p>
<p>DEST[95:64] (cid:197) Temp2[31:0]</p>
<p>DEST[127:96] (cid:197) Temp3[31:0]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p>PMULLD (128-bit Legacy SSE version)</p>
<p>Temp0[63:0] (cid:197) DEST[31:0] * SRC[31:0]</p>
<p>Temp1[63:0] (cid:197) DEST[63:32] * SRC[63:32]</p>
<p>Temp2[63:0] (cid:197) DEST[95:64] * SRC[95:64]</p>
<p>Temp3[63:0] (cid:197) DEST[127:96] * SRC[127:96]</p>
<p>DEST[31:0] (cid:197) Temp0[31:0]</p>
<p>DEST[63:32] (cid:197) Temp1[31:0]</p>
<p>DEST[95:64] (cid:197) Temp2[31:0]</p>
<p>DEST[127:96] (cid:197) Temp3[31:0]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);</p>
<p>VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);</p>
<p>VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);</p>
<p>VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);</p>
<p>VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);</p>
<p>VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);</p>
<p>VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);</p>
<p>VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);</p>
<p>PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);</p>
<p>VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);</p>
<p>VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);</p>
<p>VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);</p>
<p>VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);</p>
<p>VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);</p>
<p>VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);</p>
<p>VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);</p>
<p>VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);</p>
<p>VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type 4.</p>
<p>EVEX-encoded instruction, see Exceptions Type E4.</p></body></html>